1. Field of the Invention.
The present invention relates to an electrical circuit, and more particularly, to a signal transmission circuit and a method for equalizing disparate delay times of signal transmission paths having different delay characteristics, and a data latch circuit of a semiconductor device implementing the same.
2. Description of the Related Art.
When a signal is transmitted via a signal transmission path, it experiences a delay. The time of the delay depends on the individual characteristics and structure of the signal transmission path. Since the resistance and capacitance of the signal transmission path vary, the delay time varies. However, in a circuit such as a data latch circuit for latching data, at the point in time synchronized with a clock signal, it is necessary for two signals or more signals to be input at the same point in time. Thus, it is necessary for the delay times of signal transmission paths having different delay characteristics to be equalized.
Referring to FIG. 1, two signal transmission paths A–A′ 12 and B–B′ 14 are shown. The delay time of the A–A′ signal transmission path 12 is T1. The delay time of the B–B′ signal transmission path 14 is T2, a time less than T1. Since they are different, a compensation scheme is required for equalizing the disparate delay times T1, T2.
Referring to FIG. 2, a scheme is shown for compensating for the time difference between T1, T2. The scheme involves inserting an additional delay element into the B–B′ signal transmission path 14. The additional delay element is inverter chain 26. In another technique, the delay element is a resistance-capacitance R-C device.
The following are examples of signal transmission circuits, which have different delay characteristics.
FIG. 3A shows a case where output capacitances Ca and Cb of two signal transmission paths A–A′ and B–B′ are different. FIG. 3B shows a case where serial resistances Ra and Rb of the two signal transmission paths A–A′ and B–B′ are different. Even if capacitors C3B are similar, different R-C time constants are generated.
FIG. 3C shows a case where merely the interconnection lengths Ta and Tb of the two signal transmission paths A–A′ and B–B′ are different. This alone generates a difference in delay times. FIG. 3D shows a case where the types of gates of the two signal transmission paths A–A′ and B–B′ are different. FIG. 3E shows a case where the types of gates are similar, but the numbers are different.
FIG. 4 shows a related problem in the prior art, which is a circuit for latching by adjusting four data B1, B2, B3, B4 to one clock signal A. A clock signal A is input to four latch elements, and each of data B1 through B4 is input to one latch element corresponding to each of the data. The problem is that fan out of the input buffer for clock signal A is 4, while fan out of input buffer for each of data B1 through B4 is 1. So, the delay times of the clock signal A and the data B1 through B4 are different, because of the differential fan out between input buffer for clock and input buffer for data. In this case, data setup/hold time of each of the latch elements deteriorates. Thus, the overall operation speed decreases.
The problem of disparate delay times is pervasive. Solutions, such as those of FIG. 2 work only in part, and not continuously. That is because the delay time of an added delay device is subject to variances. The variances may arise by a difference in a semiconductor device manufacturing process, an applied voltage, and/or a temperature during operation. Accordingly, it is not easy to compensate precisely for the differences in delay time, or to maintain the compensation during operation.